Imec and Cadence Design Systems, Inc. completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System.   Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-A...